Continuum Computer Architecture for Nano-scale and Ultra-high Clock Rate Technologies

Thomas Sterling and Maciej Brodowicz (2005) Continuum Computer Architecture for Nano-scale and Ultra-high Clock Rate Technologies. In: International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, January 17-19, 2005, Oahu, Hawaii. [CaltechCACR:2005.101]

Full text available as:

PDF - Requires Adobe Acrobat Reader or other PDF viewer.

Abstract

The anticipated advent of practical nanoscale technology sometime in the next decade with likely experimental technologies nearer term presents enormous opportunities for the realization of future high performance computing potentially in the pan-Exaflops performance domain (10 18 to 10 21 flops), but imposes substantial, albeit exciting, technical challenges as well. With device density (basic components per unit area) at nanoscale predicted at least 1000X today’s commercial feature size and local clock rates expected to be at least 10X that of current generation semiconductor technology, advanced technologies will perform in an operational regime dramatically different from conventional CMOS-based microprocessors and DRAM at present.

EPrint Type:	Conference or Workshop Item (Paper)
Subjects:	All Records
ID Code:	104
Deposited By:	Sarah M. Emery
Deposited On:	20 April 2005
Record Number:	CaltechCACR:2005.101
Official Persistent URL:	http://resolver.caltech.edu/CaltechCACR:2005.101
Usage Policy:	You are granted permission for individual, educational, research and non-commercial reproduction, distribution, display and performance of this work in any format.

Archive Staff Only: edit this record